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add uart rx; 4 bytes cmd parse

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4x-tech
2025-11-17 10:13:18 +08:00
parent 5b49a0ee24
commit 6de9d53e1c
7 changed files with 237 additions and 47 deletions
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67
ti_msp_dl_config.c
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@@ -53,6 +53,7 @@ SYSCONFIG_WEAK void SYSCFG_DL_init(void)
/* Module-Specific Initializations*/
SYSCFG_DL_SYSCTL_init();
SYSCFG_DL_PWM_0_init();
SYSCFG_DL_TIMER_0_init();
SYSCFG_DL_I2C_1_init();
SYSCFG_DL_UART_0_init();
SYSCFG_DL_DMA_init();
@@ -61,6 +62,7 @@ SYSCONFIG_WEAK void SYSCFG_DL_init(void)
gPWM_0Backup.backupRdy = false;
}
/*
* User should take care to save and restore register configuration in application.
@@ -90,6 +92,7 @@ SYSCONFIG_WEAK void SYSCFG_DL_initPower(void)
DL_GPIO_reset(GPIOA);
DL_GPIO_reset(GPIOB);
DL_TimerA_reset(PWM_0_INST);
DL_TimerG_reset(TIMER_0_INST);
DL_I2C_reset(I2C_1_INST);
DL_UART_Main_reset(UART_0_INST);
@@ -98,6 +101,7 @@ SYSCONFIG_WEAK void SYSCFG_DL_initPower(void)
DL_GPIO_enablePower(GPIOA);
DL_GPIO_enablePower(GPIOB);
DL_TimerA_enablePower(PWM_0_INST);
DL_TimerG_enablePower(TIMER_0_INST);
DL_I2C_enablePower(I2C_1_INST);
DL_UART_Main_enablePower(UART_0_INST);
@@ -212,6 +216,45 @@ SYSCONFIG_WEAK void SYSCFG_DL_PWM_0_init(void) {
DL_TimerA_setCCPDirection(PWM_0_INST , DL_TIMER_CC0_OUTPUT | DL_TIMER_CC1_OUTPUT | DL_TIMER_CC2_OUTPUT );
}
/*
* Timer clock configuration to be sourced by LFCLK / (4096 Hz)
* timerClkFreq = (timerClkSrc / (timerClkDivRatio * (timerClkPrescale + 1)))
* 512 Hz = 4096 Hz / (8 * (7 + 1))
*/
static const DL_TimerG_ClockConfig gTIMER_0ClockConfig = {
.clockSel = DL_TIMER_CLOCK_LFCLK,
.divideRatio = DL_TIMER_CLOCK_DIVIDE_8,
.prescale = 7U,
};
/*
* Timer load value (where the counter starts from) is calculated as (timerPeriod * timerClockFreq) - 1
* TIMER_0_INST_LOAD_VALUE = (1 * 512 Hz) - 1
*/
static const DL_TimerG_TimerConfig gTIMER_0TimerConfig = {
.period = TIMER_0_INST_LOAD_VALUE,
.timerMode = DL_TIMER_TIMER_MODE_PERIODIC,
.startTimer = DL_TIMER_STOP,
};
SYSCONFIG_WEAK void SYSCFG_DL_TIMER_0_init(void) {
DL_TimerG_setClockConfig(TIMER_0_INST,
(DL_TimerG_ClockConfig *) &gTIMER_0ClockConfig);
DL_TimerG_initTimerMode(TIMER_0_INST,
(DL_TimerG_TimerConfig *) &gTIMER_0TimerConfig);
DL_TimerG_enableInterrupt(TIMER_0_INST , DL_TIMERG_INTERRUPT_ZERO_EVENT);
DL_TimerG_enableClock(TIMER_0_INST);
}
@@ -269,6 +312,12 @@ SYSCONFIG_WEAK void SYSCFG_DL_UART_0_init(void)
DL_UART_Main_setBaudRateDivisor(UART_0_INST, UART_0_IBRD_4_MHZ_115200_BAUD, UART_0_FBRD_4_MHZ_115200_BAUD);
/* Configure Interrupts */
DL_UART_Main_enableInterrupt(UART_0_INST,
DL_UART_MAIN_INTERRUPT_DMA_DONE_RX);
/* Configure DMA Receive Event */
DL_UART_Main_enableDMAReceiveEvent(UART_0_INST, DL_UART_DMA_INTERRUPT_RX);
/* Configure DMA Transmit Event */
DL_UART_Main_enableDMATransmitEvent(UART_0_INST);
/* Configure FIFOs */
@@ -286,7 +335,7 @@ static const DL_DMA_Config gDMA_CH0Config = {
.srcIncrement = DL_DMA_ADDR_INCREMENT,
.destWidth = DL_DMA_WIDTH_BYTE,
.srcWidth = DL_DMA_WIDTH_BYTE,
.trigger = UART_0_INST_DMA_TRIGGER,
.trigger = UART_0_INST_DMA_TRIGGER_0,
.triggerType = DL_DMA_TRIGGER_TYPE_EXTERNAL,
};
@@ -294,8 +343,24 @@ SYSCONFIG_WEAK void SYSCFG_DL_DMA_CH0_init(void)
{
DL_DMA_initChannel(DMA, DMA_CH0_CHAN_ID , (DL_DMA_Config *) &gDMA_CH0Config);
}
static const DL_DMA_Config gDMA_CH1Config = {
.transferMode = DL_DMA_FULL_CH_REPEAT_SINGLE_TRANSFER_MODE,
.extendedMode = DL_DMA_NORMAL_MODE,
.destIncrement = DL_DMA_ADDR_INCREMENT,
.srcIncrement = DL_DMA_ADDR_UNCHANGED,
.destWidth = DL_DMA_WIDTH_BYTE,
.srcWidth = DL_DMA_WIDTH_BYTE,
.trigger = UART_0_INST_DMA_TRIGGER_1,
.triggerType = DL_DMA_TRIGGER_TYPE_EXTERNAL,
};
SYSCONFIG_WEAK void SYSCFG_DL_DMA_CH1_init(void)
{
DL_DMA_initChannel(DMA, DMA_CH1_CHAN_ID , (DL_DMA_Config *) &gDMA_CH1Config);
}
SYSCONFIG_WEAK void SYSCFG_DL_DMA_init(void){
SYSCFG_DL_DMA_CH0_init();
SYSCFG_DL_DMA_CH1_init();
}